Active termination circuit and method for controlling the impedance of external integrated circuit terminals

ABSTRACT

An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

TECHNICAL FIELD

[0001] The invention relates to integrated circuits, and, moreparticularly, to a method and circuit for efficiently controlling theinput impedance of externally accessible integrated circuit terminals.

BACKGROUND OF THE INVENTION

[0002] Integrated circuits receive signals through externally accessibleinput terminals of various designs. In some integrated circuits, themagnitude of the input impedance of input terminals is not critical.Other integrated circuits, particularly memory devices operating at ahigh speed, the input impedance of at least some of the input terminalmust be controlled for optimum performance.

[0003]FIG. 1 illustrates a conventional memory device that canadvantageously use one or more embodiments of the active terminationcircuit in according to the present invention. The memory device shownin FIG. 1 is a synchronous dynamic random access memory (“SDRAM”) 10,although the active termination circuit may also be used in other memorydevices and other integrated circuits. The SDRAM 10 includes an addressregister 12 that receives either a row address or a column address on anaddress. bus 14 through an address input buffer 16. The address bus 14is generally coupled to a memory controller (not shown). Typically, arow address is initially received by the address register 12 and appliedto a row address multiplexer 18. The row address multiplexer 18 couplesthe row address to a number of components associated with either of twomemory banks 20, 22 depending upon the state of a bank address bitforming part of the row address. Associated with each of the memorybanks 20, 22 is a respective row address latch 26, which stores the rowaddress, and a row decoder 28, which applies various signals to itsrespective memory bank 20 or 22 as a function of the stored row address.The row address multiplexer 18 also couples row addresses to the rowaddress latches 26 to refresh memory cells in the memory banks 20, 22.The row addresses are generated for refresh purposes by a refreshcounter 30 that is controlled by a refresh controller 32.

[0004] After the row address has been applied to the address register 12and stored in one of the row address latches 26, a column address isapplied to the address register 12. The address register 12 couples thecolumn address to a column address latch 40. Depending on the operatingmode of the SDRAM 10, the column address is either coupled through aburst counter 42 to a column address buffer 44, or to the burst counter42 which applies a sequence of column addresses to the column addressbuffer 44 starting at the column address that is output by the addressregister 12. In either case, the column address buffer 44 supplies acolumn address to a column decoder 48 which applies various columnsignals to respective sense amplifiers and associated column circuitry50, 52 for the respective memory banks 20, 22.

[0005] Data to be read from one of the memory banks 20, 22 are coupledto the column circuitry 50, 52 for one of the memory banks 20, 22,respectively. The data are then coupled to a data output register 56which applies the data to a data bus 58 through a data input buffer 59and a data output buffer 60. Data to be written to one of the memorybanks 20, 22 are coupled from the data bus 58 through a data inputregister 62 to the column circuitry 50, 52 and then are transferredthrough word line driver circuits in the column circuitry 50, 52 to oneof the memory banks 20, 22, respectively. A mask register 64 may be usedto selectively alter the flow of data into and out of the columncircuitry 50, 52, such as by selectively masking data to be read fromthe memory banks 20, 22.

[0006] The above-described operation of the SDRAM 10 is controlled by acommand decoder 68 responsive to high level command signals received ona control bus 70 and coupled to the command decoder through a commandinput buffer 72. These high level command signals, which are typicallygenerated by a memory controller (not shown in FIG. 1), are a clockenable signal CKE*, a clock signal CLK, a chip select signal CS*, awrite enable signal WE*, a column address strobe signal CAS*, and a rowaddress strobe signal RAS*, with the “*” designating the signal asactive low or complement. The command decoder 68 generates a sequence ofcommand signals responsive to the high level command signals to carryout the function (e.g., a read or a write) designated by each of thehigh level command signals. These command signals, and the manner inwhich they accomplish their respective functions, are conventional.Therefore, in the interest of brevity, a further explanation of thesecontrol signals will be omitted

[0007] Each of the input buffers 16, 59, 72 includes a respectivetermination circuit 90 that is coupled to a respective externallyaccessible input terminal and that determines the input impedance of theinput buffer. Conventional termination circuits 90 include, for example,resistors as well as NMOS and PMOS transistors that are biased to an ONcondition. In the past, it has been difficult to efficiently control theinput impedance of the input terminals. The resistance provided bytransistors and other components can vary with process variations andoperating temperature, thus making it difficult to precisely controlinput impedance. Process variations can be compensated for to someextent by altering the circuit topography during manufacturer usingfusible links and the like. However, compensating for processingvariations in this manner increases the number of components included inthe termination circuit and may increase the number of manufacturingsteps. Furthermore, compensating for process variations in does notcompensate for temperature variations. Therefore, the input impedancecan vary with changes in temperature. Another problem with conventionaltermination circuits using PMOS or NMOS transistors is that theeffective impedance of the transistor varies with the source-to-drainvoltage, thus making the impedance of the transistor sensitive tovariations in the supply voltage.

[0008] A relatively complex circuit (not shown) can be used to implementan active termination circuit 90 that precisely controls the inputimpedance. However, providing a relatively complex termination circuit90 for each of the many input terminals of a conventional integratedcircuit, such as the SDRAM 10, greatly increases the amount of circuitryin the integrated circuit.

[0009] There is therefore a need for a circuit and method that usesrelatively little circuitry and yet is able to precisely control theinput impedance of an input terminal despite process, temperature andsupply voltage variations.

SUMMARY OF THE INVENTION

[0010] An active termination circuit and method controls the inputimpedance of a plurality of externally accessible input terminals in anintegrated circuit, such as a memory device. Each of the externallyaccessible input terminals are coupled to a respective first variableimpedance device and a respective second variable impedance device. Theimpedance of one of the first variable impedance devices is compared toa first predetermined impedance by suitable means, such as by deriving afeedback signal from a voltage divider formed by the first variableimpedance device and the first predetermined impedance. Similarly, theimpedance of one of the second variable impedance devices is compared toa second predetermined impedance by suitable means, such as by derivinga feedback signal from a voltage divider formed by the second variableimpedance device and the second predetermined impedance. Based on thesecomparisons, the impedances of all of the first variable impedancedevices and all of the second variable impedance devices are adjusted.More specifically, the impedances of all of the first variable impedancedevice are adjusted so that they have a predetermined relationship tothe first predetermined impedance, and the impedances of all of thesecond variable impedance device are adjusted so that they have apredetermined relationship to the second predetermined impedance. Thevariable impedances may each be a continuously varying impedance device,a plurality of fixed impedance devices selectively coupled in parallelwith each other, or some other variable impedance device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a block diagram of a conventional SDRAM integratedcircuit having a termination circuit coupled to each input terminal forcontrolling the input impedance of the input terminal.

[0012]FIG. 2 is a schematic of a termination circuit according to oneembodiment of the invention that may be used in the SDRAM of FIG. 1 orin another integrated circuit.

[0013]FIG. 3 is a waveform diagram showing the voltages at the variousnodes in the termination circuit of FIG. 2 responsive to variations inthe level of a supply voltage.

[0014]FIG. 4 is a schematic of a termination circuit according toanother embodiment of the invention that may be used in the SDRAM ofFIG. 1 or in another integrated circuit.

[0015]FIG. 5 is a block diagram of a computer system using the memorydevice of FIG. 1 containing the active termination circuit of eitherFIG. 2 or FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0016] One embodiment of an active termination circuit 100 is shown inFIG. 2. The active termination circuit 100 is an analog circuit thatincludes a PMOS transistor 102 a-n and an NMOS transistor 104 a-ncoupled to a respective one of a several input terminals 108 a-n of anintegrated circuit, such as the SDRAM 10 of FIG. 1. The gates of all ofthe PMOS transistors 102 a-n are coupled to each other and to a firstoutput of a control circuit 110, which provides a first output voltageV_(O1). Similarly, the gates of all of the NMOS transistors 104 a-n arecoupled to each other and to a second output of the control circuit 110,which provides a second output voltage V_(O2). By using only twotransistors 102 a-n, 104 a-n for each input terminal 108 a-n and asingle control circuit 110 to provide signals to all of the transistors102 a-n, 104 a-n, relatively little circuitry is required to control theinput impedance of all of the input terminals 108 a-n. The manner inwhich the output voltages V_(O1) and V_(O2) are adjusted to maintain aconstant input impedance at the input terminals 108 a-n despite processvariations and variations in the temperature and supply voltage V_(CC)will be explained with the explanation of the control circuit 110.

[0017] The control circuit 110 includes a differential amplifier 112formed by a pair of NMOS input transistors 120, 122, a pair of PMOS loadtransistors 126, 128 coupled as a current mirror, and an NMOS transistor130 that draws a constant current collectively through the inputtransistors 120, 122. An output of the differential amplifier 112 iscoupled to the gate of a PMOS transistor 134 and to the input of abuffer 136. An output of the buffer 136 is coupled to the gate of eachPMOS transistor 102 a-n, as previously explained.

[0018] The PMOS transistor 134 is coupled in series with a resistor 138between a supply voltage V_(CC) and ground. The PMOS transistor 134 andresistor 138 form a voltage divider that generates a feedback voltageV_(F), which is applied to the gate of the input transistor 122. Thegate of the other input transistor 120 is coupled to a reference voltageV_(REF), which may be one-half the supply voltage V_(CC) but may alsohave other values.

[0019] The control circuit 110 also includes a second differentialamplifier 142 that uses the same components as the differentialamplifier 112 operating in the same manner and provided with the samereference numerals. A first output of the differential amplifier 142 iscoupled to the gate of an NMOS transistor 144 and to the input of abuffer 146. The output of the buffer 146 is coupled to the gate of eachNMOS transistor 104 a-n, as also previously explained.

[0020] The NMOS transistor 144 is coupled in series with a resistor 148between a supply voltage V_(CC) and ground to form a voltage divider. Afeedback voltage V_(F) generated by the voltage divider is coupled tothe gate of one input transistor 122 in the differential amplifier 142.The gate of the other input transistor 120 of the differential amplifier142 is coupled to a reference voltage V_(REF). Note, however, that theorder of the PMOS transistor 134 and the resistor 138 forming the firstvoltage divider is the reverse of the order of the NMOS transistor 144and the resistor 148 forming the second voltage divider. As a result,the first output voltage V_(O1) decreases with increases in theresistance of the PMOS transistor 134 while the second output voltageV_(O2) increases with increases in the resistance of the NMOS transistor144.

[0021] In operation, the differential amplifier 112 adjusts the outputvoltage V_(O1) so that the PMOS transistor 134 has a resistance thatcauses the feedback voltage V_(F) to be equal to the reference voltageV_(REF). If the reference voltage V_(REF) is equal to one-half thesupply voltage V_(CC), the impedance of the PMOS transistor 134 will beequal to the resistance of the resistor 138. An increase in theimpedance of the PMOS transistor 134 causes a decrease in the feedbackvoltage V_(F), which will cause the differential amplifier 112 todecrease the output voltage V_(O1). The reduced output voltage V_(O1)coupled to the gate of the PMOS transistor 134 decreases the impedanceof the PMOS transistor 134 so that the magnitude of the feedback voltageV_(F) again equals the magnitude of the reference voltage V_(REF).

[0022] The differential amplifier 142 operates in essentially the samemanner to maintain the impedance of the NMOS transistor 144 equal to theresistance of the resistor 148. More specifically, any decrease in theimpedance of the NMOS transistor 144 causes a decrease in the magnitudeof the feedback voltage V_(F). The differential amplifier 142 respondsto the decreased feedback voltage V_(F) by decreasing the output voltageV_(O2) , which causes the impedance of the NMOS transistor 144 toincrease until the magnitude of the feedback voltage V_(F) is againequal to the magnitude of the reference voltage V_(REF).

[0023] Although the control circuit 110 has been explained with respectto the magnitude of the reference voltage V_(REF) being one-half themagnitude of the supply voltage V_(CC), it will be understood that themagnitude of the reference voltage and the supply voltage may have otherrelationships. For example, if the magnitude of the reference voltageV_(REF) is equal to two-thirds of the supply voltage V_(CC), theimpedance of the PMOS transistor will be one-half the resistance of theresistor 138, and the impedance of the NMOS transistor 144 will beone-half the resistance of the resistor 148. As long as the resistanceof the resistors 138, 148 are equal to each other, the impedance of thePMOS transistor 134 will still be equal to the impedance of the NMOStransistor 144.

[0024] Although the electrical characteristics of the PMOStransistors—102 a-n and the NMOS transistors 104 a-n may vary withprocess variations, temperature and supply voltage the same electricalcharacteristics of the PMOS transistor 134 and the NMOS transistor 144can be expected to vary with process variations in substantially thesame manner. Therefore, the active termination circuit 100 will besubstantially insensitive to process, temperature and supply voltagevariations.

[0025] The manner in which the active termination circuit 100 isinsensitive to variations in the supply voltage V_(CC) will now beexplained with reference to FIGS. 3A-G. When the supply voltage V_(CC)is 1.6 volts as shown in FIG. 3A and the reference voltage V_(REF) isone-half V_(CC), or 0.8 volts, as shown in FIG. 3B, the feedback voltageVF will also be one-half V_(CC), or 0.8 volts, as shown in FIG. 3C. Insuch case, the output voltage V_(O1) will be adjusted by thedifferential amplifier 112 to 1.24 volts, as shown in FIG. 3D, which isthe voltage needed to make the impedance of the PMOS transistor 134equal to the resistance of the resistor 138. In a similar manner, thedifferential amplifier 142 will generate a voltage V_(O2) of 0.38 volts,as shown in FIG. 3E, which is the voltage needed to make the impedanceof the NMOS transistor 144 equal to the resistance of the resistor 148.The impedance of the PMOS transistors 102 will then be approximatelyequal to the impedance of the NMOS transistors 104, so that the voltageV_(OUT) on the input terminals 108 will be equal to approximatelyone-half V_(CC), or 0.8 volts. As shown in FIG. 3F, in one embodimentthis voltage is 0.808 volts. Finally, the current I_(O) through eachseries combination of a PMOS transistor 102 and a respective NMOStransistor 104 will be 2.66 ma, as shown in FIG. 3G.

[0026] The impedance of each PMOS transistor 102 and each NMOStransistor 104 is equal to the voltage across each of the transistors102, 104 divided by the current through the transistors 102, 104. Forthe PMOS transistors 102, the voltage across the transistors 102 is0.792 volts, so that the impedance of the PMOS transistors 102 can becalculated by the ratio of 0.792 volts to 2.66 ma as 298 ohms. In asimilar manner, the impedance of the NMOS transistors 104 can becalculated as the ratio of the 0.808 volts across the transistors 104 tothe 2.66 ma of current through the transistors 104, or 304 ohms. Theinput impedance of the input terminals 108 will thus be the impedance ofthe two transistors 102, 104 in parallel, or substantially 150 ohms.

[0027] If the supply voltage V_(CC) increases to 1.8 volts as shown inFIG. 3A, the reference voltage and the feedback voltage will increaseaccordingly so that the differential amplifier 112 will then generate anoutput voltage V_(O1) equal to 1.29 volts and the differential amplifier142 will generate an output voltage V_(O2) equal to 0.54 volts, as shownin FIGS. 3D and E, respectively. Although the voltage applied to thegate of the PMOS transistor 134 increases from 1.24 volts to 1.29 volts,i.e., by 0.05 volts, the supply voltage VCC has increased to a greaterextent, i.e. from 1.6 volts to 1.8 volts, or an increase in 0.2 volts.As a result, the gate-to-source of voltage of the PMOS transistor 134increases by 0.15 volts, i.e. 0.2 volts less 0.05 volts. This increasedgate-to-source of voltage increases the current through the transistor134 to 3 ma, as shown in FIG. 3G. However, since the voltage on theinput terminal 108 has increased to 0.906 volts, as shown in FIG. 3F,the voltage across the PMOS transistor 134 has increased to 0.894 volts.The impedance of the PMOS transistors 102 can then be calculated by theratio of 0.894 volts to 3 ma as 298 ohms, which is the same impedancepreviously calculated for a supply voltage V_(CC) of 1.6 volts.Similarly, the impedance of each NMOS transistor 104 can be calculatedby the ratio of the 0.906 volts across the transistor 104 to the 3 ma ofcurrent through the transistor 104 as 302 ohms, which is substantiallythe same impedance as the 304 ohms calculated for a supply voltageV_(CC) of 1.6 volts.

[0028] If the supply voltage V_(CC) increases to 2 volts as shown inFIG. 3A, the impedance of each PMOS transistor 102 can be calculated inthe same manner as described above to be 299 ohms, i.e., 1 volt acrossthe transistor 102 divided by 3.34 ma. The impedance of each NMOStransistor 104 can be calculated in the same manner as described aboveto also be 299 ohms, i.e., 1 volt across the transistor 104 divided by3.34 ma. It can therefore be seen that the input impedance at each inputterminal 108 is substantially insensitive to variations in the supplyvoltage V_(CC).

[0029] Another embodiment of an active termination circuit 200 is shownin FIG. 4. Unlike the analog active termination circuit 100 of FIG. 2,the active termination circuit of FIG. 4 is a digital circuit. Eachinput terminal 8 a-n is coupled to the drains of a set of PMOStransistors 204 a-n that are coupled to each other in parallel, and tothe drains of a set of NMOS transistors 208 a-n that are coupled to eachother in parallel. The sources of the PMOS transistors 204 a-n arecoupled to a supply voltage V_(CC) while the sources of the NMOStransistors 208 a-n are coupled to ground. The gates of the PMOStransistors 204 a-n are coupled to a first control circuit 210 while thegates of the NMOS transistors 208 a-n are coupled to a second controlcircuit 216.

[0030] In operation, the voltage at each input terminal 8 a-n isdetermined by the impedance of the parallel combination of PMOStransistors 204 a-n relative to the impedance of the parallelcombination of NMOS transistors 208 a-n. A set of PMOS transistors 204a-n and a set of NMOS transistors 208 a-n are provided for each inputterminal 8 a-n. The input impedance at the input terminal 8 a-n isdetermined by the parallel combination of the PMOS transistors 204 a-nand the parallel combination of the NMOS transistors 208 a-n in parallelwith each other. As explained in detail below, the first control circuit210 selectively turns ON a plurality of the PMOS transistors 204 a-n andthe second control circuit 216 selectively turns ON a plurality of theNMOS transistors 208 a-n so that both the impedance of the parallelcombination of PMOS transistors 204 a-n and the impedance of theparallel combination of NMOS transistors 208 a-n are substantially equalto a predetermined impedance. As a result, the input impedance at theinput terminal 8 a-n are set to predetermine values.

[0031] The first control circuit 210 and the second control circuit 216are substantially identical in structure and function. The onlysignificant difference between the first control circuit 210 and thesecond control circuit 216 is that the first control circuit 210includes a parallel combination of PMOS transistors 220 coupled betweenthe supply voltage V_(CC) and a resistor 222 that is coupled to ground,while the second control circuit 216 includes a parallel combination ofNMOS transistors 226 coupled between ground and a resistor 228 that iscoupled to the supply voltage V_(CC).

[0032] Each of the control circuits 210, 216 includes a first comparator230 and a second comparator 232. A feedback voltage V_(F) is applied tothe “+” input of the first comparator 230 into the “−” input of thesecond comparator 232. The first comparator 230 also receives a firstreference voltage V_(REF+) while the second comparator 232 also receivesa second reference voltage V_(REF−). The magnitude of the firstreference voltage V_(REF+) is slightly larger than the magnitude of thesecond reference voltage V_(REF−). As explained below, the differencebetween the magnitude of the first reference voltage and the magnitudeof the second reference voltage V_(REF−) establishes a deadband. In theactive termination circuit 200 of FIG. 4, the deadband is preferablycentered at a voltage that is approximately one-half the supply voltageV_(CC). When the feedback voltage V_(F) is within the deadband, thenumber of transistors 220, 226 that are switched ON does not change.When the feedback voltage V_(F) is outside the deadband, the number oftransistors 220, 226 that are switched ON is either increased ordecreased depending upon whether the feedback voltage V_(F) is above orbelow the deadband.

[0033] Outputs from the comparators 230, 232 are applied to an input ofa respective NAND-gate 236, 238. An input of each NAND-gate 236, 238also receives an output from an oscillator 240. Respective outputs fromthe NAND-gates 236, 238 are applied to an up/down counter 246. However,the output from the NAND-gate 236 is applied to the “DN” input of thecounter 246 in the first control circuit 210 and to the “UP” input ofthe counter 246 in the second control circuit 216. Also, the output fromthe NAND-gate 238 is applied to the “UP” input of the counter 246 in thefirst control circuit 210 and to the “DN” input of the counter 246 inthe second control circuit 216.

[0034] The operation of the control circuits 210, 216 will now beexplained with initial reference to the first control circuit 210. Whenthe magnitude of the feedback voltage V_(F) is greater than themagnitude of the reference voltage V_(REF+), the NAND-gate 236 isenabled by a high output from the comparator 230 resulting from thepositive comparison between the feedback voltage V_(F) and the referencevoltage V_(REF+). As a result, pulses from the oscillator 240 arecoupled through the NAND-gate 236 to the “DN” input of the counter 246.The counter 246 then decrements its count. The ON impedance of the PMOStransistors 220 preferably vary from each other in a binary manner sothat the ON impedance of the leftmost PMOS transistor 220 is one-halfthe ON impedance of the PMOS transistor 220 to its right, and the ONimpedance of the rightmost PMOS transistor 220 is twice the ON impedanceof the PMOS transistor 220 to its left. The PMOS transistors 204 a-ncoupled to the input terminals 108 a-n vary in the same manner. As aresult, the impedance of the parallel combination of PMOS transistors220 and 204 a-n will correspond to the count of the counter 246.Therefore, when the counter 246 is decremented responsive to thefeedback voltage V_(F) being greater than the reference voltageV_(REF+), as previously explained, the impedance of the parallelcombination of PMOS transistors 220 and 204 a-n is increased. When theimpedance of the PMOS transistors 220 is increased, the feedback voltageV_(F) will be reduced to some voltage that is within the deadband.

[0035] The control circuit 210 responds to the feedback voltage V_(F)being below the deadband in a similar manner. Specifically, when themagnitude of the feedback voltage V_(F) is less than the magnitude ofthe reference voltage V_(REF−), the NAND-gate 238 is enabled by thepositive comparison between the reference voltage V_(REF−) and thefeedback voltage V_(F). As result, pulses from the oscillator 240 aregated to the “UP” input of the counter 246. The count of the counter 246is then incremented, thereby turning ON additional PMOS transistors 220and 204 a-n. The additional PMOS transistors 220 that are turned ONincrease the feedback voltage until it is at a voltage that is withinthe deadband.

[0036] As mentioned above, the deadband is preferably centered atone-half the magnitude of the supply voltage V_(CC). When the feedbackvoltage V_(F) is centered in the deadband, i.e. is at one-half V_(CC),the impedance of the parallel combination of PMOS transistors 220 and204 a-n will be equal to the resistance of the resistor 222. The PMOStransistors 204 a-n coupled to the input terminals 8 a-n are identicalto and fabricated in the same process as the PMOS transistors 220. Theimpedance of each parallel combination of PMOS transistors 204 a-n willtherefore also be equal to the resistance of the resistor 222.

[0037] The control circuit 216 operates in substantially the same manneras the control circuit 210. As in the control circuit 210, when themagnitude of the feedback voltage V_(F) is greater than the magnitude ofthe reference voltage V_(REF+), the NAND-gate 236 will be enabled, andwhen the magnitude of the feedback voltage V_(F) is less than themagnitude of the reference voltage V_(REF−), the NAND-gate 238 will beenabled. When the magnitude of the feedback voltage V_(F) is greaterthan the magnitude of the reference voltage V_(REF+), the counter 246will be incremented to increase the number of NMOS transistors 226 thatare turned ON. The impedance of the parallel combination of NMOStransistors 226 and 208 a-n will therefore be decreased, which willreduce the magnitude of the feedback voltage V_(F) so that it is withinthe deadband. When the magnitude of the feedback voltage V_(F) is lessthan the magnitude of the reference voltage V_(REF−), the counter 246will be decremented to decrease the number of NMOS transistors 226 thatare turned ON. The impedance of the parallel combination of NMOStransistors 226 and 208 a-n will therefore be increased, which willincrease the magnitude of the feedback voltage V_(F) SO that it iswithin the deadband. In this manner, the impedance of the parallelcombination of NMOS transistors 226 and 208 a-n, will be set to equalthe resistance of the resistor 228. Assuming the resistances of theresistors to 222, 228 are equal to each other, the impedance of eachparallel combination of PMOS transistors 204 a-n coupled to a respectiveinput terminal 8 a-n will be equal to the impedance of the parallelcombination of NMOS transistors 208 a-n coupled to the same inputterminal 8 a-n.

[0038] As with the active termination circuits 100 of FIG. 2, the activetermination circuit 200 of FIG. 4 can precisely control the impedanceand bias voltage level at each input terminal 8 a-n using only a singlepair of control circuits 210, 216 for all of the input terminals 8 a-n.Furthermore, as long as the reference voltages track changes in thesupply voltage V_(CC), such as by being generated from the supplyvoltage V_(CC) using a voltage divider, the input impedance at eachinput terminal 8 a-n will be insensitive to changes in the supplyvoltage V_(CC). Finally, since the PMOS transistors 204 a-n areidentical to and fabricated in the same process as the PMOS transistors220, and the NMOS transistors 208 a-n are identical to and fabricated inthe same process as the NMOS transistors 226, the impedance at eachinput terminal 8 a-n are substantially insensitive to processvariations.

[0039]FIG. 5 illustrates an example of a computer system 300 using theSDRAM 10 of FIG. 1 with active termination circuits coupled to at leastsome of its externally accessible input terminals according to oneembodiment of the invention. the computer system includes a processor302 for performing various computing functions, such as executingspecific software to perform specific calculations or tasks. Theprocessor 302 includes a processor bus 304 that normally includes theaddress bus 14, the data bus 58, and the control bus 70. In addition,the computer system 300 includes one or more input devices 314, such asa keyboard or a mouse, coupled to the processor 302 to allow an operatorto interface with the computer system 300. Typically, the computersystem 300 also includes one or more output devices 316 coupled to theprocessor 302, such output devices typically being a printer or a videoterminal. One or more data storage devices 318 are also typicallycoupled to the processor 302 to allow the processor 302 to store data orretrieve data from internal or external storage media (not shown).Examples of typical storage devices 318 include hard and floppy disks,tape cassettes and compact disk read-only memories (CD-ROMs). Theprocessor 302 is also typically coupled to cache memory 326, which isusually static random access memory (“SRAM”) and to the SDRAM 10 througha memory controller 330. The memory controller 330 normally includes thecontrol bus 70 and the address bus 14 that is coupled to the SDRAM 10.The data bus 58 may be coupled to the processor bus 304 either directly(as shown), through the memory controller 330, or by some other means.Although the computer system 300 shown in FIG. 5 uses SDRAM memorydevices, it will be understood that computer systems may alternativelyuse other types of memory devices having externally accessible inputterminals that are coupled to an active termination circuit according tovarious embodiments of the invention. Also, the input terminals of theprocessor 302 may include active termination circuit according tovarious embodiments of the invention.

[0040] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. For example, it may be possibleto use a fixed impedance element, such as a resistor, having arelatively high impedance coupled to the power supply voltage in placeof either the PMOS transistor(s) or coupled to ground in place of eitherthe NMOS transistor(s). The impedance of the input terminal could thenbe controlled by the lower impedance NMOS or PMOS transistor(s).Accordingly, the invention is not limited except as by the appendedclaims.

1. An active termination circuit for setting the input impedance of aplurality of input terminals to a predetermined value, the activetermination circuit comprising: a first controllable impedance devicecoupled between a first supply voltage and a respective one of the inputterminals, the impedance of the first controllable impedance devicebeing controlled by a first impedance control signal; a secondcontrollable impedance device coupled between a second supply voltageand a respective one of the input terminals, the impedance of the secondcontrollable impedance device being controlled by a second impedancecontrol signal; a first control circuit coupled to provide the firstimpedance control signal to all of the first controllable impedancedevices, the first control circuit comprising: a third controllableimpedance device coupled between a third supply voltage and a firstfeedback node, the impedance of the third controllable impedance devicebeing controlled by the first impedance control signal; a firstpredetermined resistance coupled between the first feedback node and afourth supply voltage, the third controllable impedance device and thefirst predetermined resistance forming a voltage divider between thethird and fourth supply voltages to produce a first feedback voltage atthe first feedback node; and a first comparator circuit comparing thefirst feedback voltage to a first reference voltage, the firstcomparator circuit causing the first impedance control signal to vary sothat the first feedback voltage is substantially equal to the firstreference voltage; and a second control circuit coupled to provide thesecond impedance control signal to all of the second controllableimpedance devices, the second control circuit comprising: a secondpredetermined resistance coupled between a fifth supply voltage and asecond feedback node, a fourth controllable impedance device coupledbetween the second feedback node and a sixth supply voltage, theimpedance of the fourth controllable impedance device being controlledby the second impedance control signal, the second predeterminedresistance and the fourth controllable impedance device forming avoltage divider between the fifth and sixth supply voltages to produce asecond feedback voltage at the second feedback node; and a secondcomparator circuit comparing the second feedback voltage to a secondreference voltage, the second comparator circuit causing the secondimpedance control signal to vary so that the second feedback voltage issubstantially equal to the second reference voltage.
 2. The activetermination circuit of claim 1, wherein the first, third and fifthsupply voltages comprise a power supply voltage, and wherein the second,fourth, and sixth supply voltages comprise ground potential.
 3. Theactive termination circuit of claim 2 wherein the first and secondreference voltages comprise one-half the power supply voltage.
 4. Theactive termination circuit of claim 1 wherein the first controllableimpedance device and the third controllable impedance device compriseidentical controllable impedance devices.
 5. The active terminationcircuit of claim 4 wherein the first controllable impedance device andthe third controllable impedance device comprise identical MOSFETtransistors.
 6. The active termination circuit of claim 1 wherein thesecond controllable impedance device and the fourth controllableimpedance device comprise identical controllable impedance devices. 7.The active termination circuit of claim 6 wherein the first controllableimpedance device and the third controllable impedance device compriseidentical MOSFET transistors.
 8. The active termination circuit of claim1 wherein: the first comparator circuit comprises a first differentialamplifier generating a first comparison signal corresponding to thedifference between the first feedback signal and the first referencesignal, the first impedance control signal corresponding to the firstcomparison signal; and the second comparator circuit comprises a seconddifferential amplifier generating a first comparison signalcorresponding to the difference between the second feedback signal andthe second reference signal, the second impedance control signalcorresponding to the second comparison signal.
 9. The active terminationcircuit of claim 1 wherein the first controllable impedance device andthe third controllable impedance device each comprise a plurality ofMOSFET transistors coupled in parallel with each other, and wherein thefirst impedance control signal selectively turns ON a variable number ofthe MOSFET transistors in each plurality to alter the impedance of thefirst and third controllable impedance devices.
 10. The activetermination circuit of claim 1 wherein the controllable impedancedevices comprises respective voltage controlled impedance devices. 11.An active termination circuit for setting the input impedance of aplurality of input terminals to a predetermined value, the activetermination circuit comprising: a first controllable impedance devicecoupled between a first supply voltage and a respective one of the inputterminals, the impedance of the first controllable impedance devicebeing controlled by an impedance control signal; an impedance devicecoupled between a second supply voltage and a respective one of theinput terminals; a control circuit coupled to provide the impedancecontrol signal to all of the first controllable impedance devices, thefirst control circuit comprising: a second controllable impedance devicecoupled between a third supply voltage and a feedback node, theimpedance of the second controllable impedance device being controlledby the impedance control signal; a predetermined resistance coupledbetween the feedback node and a fourth supply voltage, the secondcontrollable impedance device and the predetermined resistance forming avoltage divider between the third and fourth supply voltages to producea feedback voltage at the feedback node; and a comparator circuitcomparing the feedback voltage to a reference voltage, the comparatorcircuit causing the impedance control signal to vary so that thefeedback voltage is substantially equal to the reference voltage. 12.The active termination circuit of claim 11 wherein each of the impedancedevices comprise a third controllable impedance device, the impedance ofthe third controllable impedance device being controlled by a secondimpedance control signal.
 13. The active termination circuit of claim 11wherein the first and third supply voltages comprise a power supplyvoltage, and wherein the second and fourth supply voltages compriseground potential.
 14. The active termination circuit of claim 13 whereinthe reference voltage comprise one-half the power supply voltage. 15.The active termination circuit of claim 11 wherein the firstcontrollable impedance device and the second controllable impedancedevices comprise identical controllable impedance devices.
 16. Theactive termination circuit of claim 15 wherein the first controllableimpedance device and the second controllable impedance device compriseidentical MOSFET transistors.
 17. The active termination circuit ofclaim 11 wherein the comparator circuit comprises a differentialamplifier generating a comparison signal corresponding to the differencebetween the feedback signal and the reference signal, the impedancecontrol signal corresponding to the comparison signal.
 18. The activetermination circuit of claim 11 wherein the first controllable impedancedevice and the second controllable impedance device each comprise aplurality of MOSFET transistors coupled in parallel with each other, andwherein the impedance control signal selectively turns ON a variablenumber of the MOSFET transistors in each plurality to alter theimpedance of the first and second controllable impedance devices. 19.The active termination circuit of claim 11 wherein the controllableimpedance devices comprises respective voltage controlled impedancedevices.
 20. An active termination circuit for setting the inputimpedance of a plurality of input terminals to a predetermined value,the active termination circuit comprising: at least one PMOS transistorcoupled between a first supply voltage and a respective one of the inputterminals, the impedance of the at least one PMOS transistor beingcontrolled by a first impedance control signal; at least one NMOStransistor coupled between a second supply voltage and a respective oneof the input terminals, the impedance of the at least one NMOStransistor being controlled by a second impedance control signal; afirst control circuit coupled to provide the first impedance controlsignal to all of the PMOS transistors, the first control circuitcomprising: at least one PMOS transistor coupled between the firstsupply voltage and a first feedback node, the impedance of the at leastone PMOS transistor being controlled by the first impedance controlsignal; a first predetermined resistance coupled between the firstfeedback node and the second supply voltage, the at least one PMOStransistor and the first predetermined resistance forming a voltagedivider between the first and second supply voltages to produce a firstfeedback voltage at the first feedback node; and a first comparatorcircuit comparing the first feedback voltage to a first referencevoltage, the first comparator circuit causing the first impedancecontrol signal to vary to control the impedance of the at least one PMOStransistor so that the first feedback voltage is substantially equal tothe first reference voltage; and a second control circuit coupled toprovide the second impedance control signal to the at least one NMOStransistor, the second control circuit comprising: a secondpredetermined resistance coupled between the first supply voltage and asecond feedback node, at least one NMOS transistor coupled between thesecond feedback node and the second supply voltage, the impedance of theat least one NMOS transistor being controlled by the second impedancecontrol signal, the second predetermined resistance and the at least oneNMOS transistor forming a voltage divider between the first and secondsupply voltages to produce a second feedback voltage at the secondfeedback node; and a second comparator circuit comparing the secondfeedback voltage to a second reference voltage, the second comparatorcircuit causing the second impedance control signal to vary to controlthe impedance of the at least one PMOS transistor so that the secondfeedback voltage is substantially equal to the second reference voltage21. The active termination circuit of claim 20 wherein the first supplyvoltages comprises a power supply voltage, and wherein the second supplyvoltage comprises ground potential.
 22. The active termination circuitof claim 21 wherein the first and second reference voltages compriseone-half the power supply voltage.
 23. The active termination circuit ofclaim 20 wherein the at least one PMOS transistor coupled to respectiveinput terminals are substantially to each other and to the at least onePMOS transistor in the first control circuit, and wherein the at leastone NMOS transistor coupled to respective input terminals aresubstantially to each other and to the at least one NMOS transistor inthe second control circuit.
 24. The active termination circuit of claim20 wherein the at least one PMOS transistor in the first control circuitand the at least one PMOS transistor coupled to each input terminal eachcomprise a single PMOS transistor, wherein the at least one NMOStransistor in the second control circuit and the at least one NMOStransistor coupled to each input terminal each comprise a single NMOStransistor, and wherein the first and second impedance control signalscomprise respective analog signals.
 25. The active termination circuitof claim 20 wherein the at least one PMOS transistor in the firstcontrol circuit and the at least one PMOS transistor coupled to eachinput terminal each comprise a plurality of PMOS transistors coupled inparallel to each other, wherein the at least one NMOS transistor in thesecond control circuit and the at least one NMOS transistor coupled toeach input terminal each comprise a plurality of NMOS transistorscoupled in parallel to each other, and wherein the first and secondimpedance control signals comprise respective signals that selectivelyturn ON a variable number of the PMOS and NMOS transistors.
 26. Theactive termination circuit of claim 20 wherein: the first comparatorcircuit comprises a first differential amplifier generating a firstcomparison signal corresponding to the difference between the firstfeedback signal and the first reference signal, the first impedancecontrol signal corresponding to the first comparison signal; and thesecond comparator circuit comprises a second differential amplifiergenerating a first comparison signal corresponding to the differencebetween the second feedback signal and the second reference signal, thesecond impedance control signal corresponding to the second comparisonsignal.
 27. A memory device, comprising: a command decoder receivingmemory command signals through externally accessible command inputterminals, the command decoder generating memory control signalsresponsive to predetermined combinations of the command signals; anaddress decoder receiving address signals through externally accessibleaddress input terminals, the address decoder generating row and columnaddressing signals responsive to the address signals; at least onememory array, the at least one memory array writing data to and readingdata from locations corresponding the address signals responsive to thememory control signals; a data path extending between a plurality ofexternally accessible data bus terminals and the memory array forcoupling data signals to and from the memory array; and an activetermination circuit for setting the input impedance of plurality of theexternally accessible terminals to a predetermined value, the activetermination circuit comprising: a first controllable impedance devicecoupled between a first supply voltage and a respective one of the inputterminals, the impedance of the first controllable impedance devicebeing controlled by a first impedance control signal; a secondcontrollable impedance device coupled between a second supply voltageand a respective one of the input terminals, the impedance of the secondcontrollable impedance device being controlled by a second impedancecontrol signal; a first control circuit coupled to provide the firstimpedance control signal to all of the first controllable impedancedevices, the first control circuit comprising: a third controllableimpedance device coupled between a third supply voltage and a firstfeedback node, the impedance of the third controllable impedance devicebeing controlled by the first impedance control signal; a firstpredetermined resistance coupled between the first feedback node and afourth supply voltage, the third controllable impedance device and thefirst predetermined resistance forming a voltage divider between thethird and fourth supply voltages to produce a first feedback voltage atthe first feedback node; and a first comparator circuit comparing thefirst feedback voltage to a first reference voltage, the firstcomparator circuit causing the first impedance control signal to vary sothat the first feedback voltage is substantially equal to the firstreference voltage; and a second control circuit coupled to provide thesecond impedance control signal to all of the second controllableimpedance devices, the second control circuit comprising: a secondpredetermined resistance coupled between a fifth supply voltage and asecond feedback node, a fourth controllable impedance device coupledbetween the second feedback node and a sixth supply voltage, theimpedance of the fourth controllable impedance device being controlledby the second impedance control signal, the second predeterminedresistance and the fourth controllable impedance device forming avoltage divider between the fifth and sixth supply voltages to produce asecond feedback voltage at the second feedback node; and a secondcomparator circuit comparing the second feedback voltage to a secondreference voltage, the second comparator circuit causing the secondimpedance control signal to vary so that the second feedback voltage issubstantially equal to the second reference voltage.
 28. The memorydevice of claim 27 wherein the command and address signals are coupledto the memory device in a packet containing both the command signals andthe address signals.
 29. The memory device of claim 27 wherein thefirst, third and fifth supply voltages comprise a power supply voltage,and wherein the second, fourth, and sixth supply voltages compriseground potential.
 30. The memory device of claim 29 wherein the firstand second reference voltages comprise one-half the power supplyvoltage.
 31. The memory device of claim 27 wherein the firstcontrollable impedance device and the third controllable impedancedevice comprise identical controllable impedance devices.
 32. The memorydevice of claim 31 wherein the first controllable impedance device andthe third controllable impedance device comprise identical MOSFETtransistors.
 33. The memory device of claim 27 wherein the secondcontrollable impedance device and the fourth controllable impedancedevice comprise identical controllable impedance devices.
 34. The memorydevice of claim 33 wherein the first controllable impedance device andthe third controllable impedance device comprise identical MOSFETtransistors.
 35. The memory device of claim 27 wherein: the firstcomparator circuit comprises a first differential amplifier generating afirst comparison signal corresponding to the difference between thefirst feedback signal and the first reference signal, the firstimpedance control signal corresponding to the first comparison signal;and the second comparator circuit comprises a second differentialamplifier generating a first comparison signal corresponding to thedifference between the second feedback signal and the second referencesignal, the second impedance control signal corresponding to the secondcomparison signal.
 36. The memory device of claim 27 wherein the firstcontrollable impedance device and the third controllable impedancedevice each comprise a plurality of MOSFET transistors coupled inparallel with each other, and wherein the first impedance control signalselectively turns ON a variable number of the MOSFET transistors in eachplurality to alter the impedance of the first and third controllableimpedance devices.
 37. The memory device of claim 27 wherein the memorydevice comprises a dynamic random access memory.
 38. The memory deviceof claim 27 wherein the dynamic random access memory comprises asynchronous dynamic random access memory.
 39. The memory device of claim27 wherein the controllable impedance devices comprises respectivevoltage controlled impedance devices.
 40. A memory device, comprising: acommand decoder receiving memory command signals through externallyaccessible command input terminals, the command decoder generatingmemory control signals responsive to predetermined combinations of thecommand signals; an address decoder receiving address signals throughexternally accessible address input terminals, the address decodergenerating row and column addressing signals responsive to the addresssignals; at least one memory array, the at least one memory arraywriting data to and reading data from locations corresponding theaddress signals responsive to the memory control signals; a data pathextending between a plurality of externally accessible data busterminals and the memory array for coupling data signals to and from thememory array; and an active termination circuit for setting the inputimpedance of plurality of the externally accessible terminals to apredetermined value, the active termination circuit comprising: at leastone PMOS transistor coupled between a first supply voltage and arespective one of the input terminals, the impedance of the at least onePMOS transistor being controlled by a first impedance control signal; atleast one NMOS transistor coupled between a second supply voltage and arespective one of the input terminals, the impedance of the at least oneNMOS transistor being controlled by a second impedance control signal; afirst control circuit coupled to provide the first impedance controlsignal to all of the PMOS transistors, the first control circuitcomprising: at least one PMOS transistor coupled between the firstsupply voltage and a first feedback node, the impedance of the at leastone PMOS transistor being controlled by the first impedance controlsignal; a first predetermined resistance coupled between the firstfeedback node and the second supply voltage, the at least one PMOStransistor and the first predetermined resistance forming a voltagedivider between the first and second supply voltages to produce a firstfeedback voltage at the first feedback node; and a first comparatorcircuit comparing the first feedback voltage to a first referencevoltage, the first comparator circuit causing the first impedancecontrol signal to vary to control the impedance of the at least one PMOStransistor so that the first feedback voltage is substantially equal tothe first reference voltage; and a second control circuit coupled toprovide the second impedance control signal to the at least one NMOStransistor, the second control circuit comprising: a secondpredetermined resistance coupled between the first supply voltage and asecond feedback node, at least one NMOS transistor coupled between thesecond feedback node and the second supply voltage, the impedance of theat least one NMOS transistor being controlled by the second impedancecontrol signal, the second predetermined resistance and the at least oneNMOS transistor forming a voltage divider between the first and secondsupply voltages to produce a second feedback voltage at the secondfeedback node; and a second comparator circuit comparing the secondfeedback voltage to a second reference voltage, the second comparatorcircuit causing the second impedance control signal to vary to controlthe impedance of the at least one PMOS transistor so that the secondfeedback voltage is substantially equal to the second reference voltage41. The memory device of claim 40 wherein the command and addresssignals are coupled to the memory device in a packet containing both thecommand signals and the address signals.
 42. The memory device of claim40 wherein the first supply voltages comprises a power supply voltage,and wherein the second supply voltage comprises ground potential. 43.The memory device of claim 42 wherein the first and second referencevoltages comprise one-half the power supply voltage.
 44. The memorydevice of claim 40 wherein the at least one PMOS transistor coupled torespective input terminals are substantially to each other and to the atleast one PMOS transistor in the first control circuit, and wherein theat least one NMOS transistor coupled to respective input terminals aresubstantially to each other and to the at least one NMOS transistor inthe second control circuit.
 45. The memory device of claim 40 whereinthe at least one PMOS transistor in the first control circuit and the atleast one PMOS transistor coupled to each input terminal each comprise asingle PMOS transistor, wherein the at least one NMOS transistor in thesecond control circuit and the at least one NMOS transistor coupled toeach input terminal each comprise a single NMOS transistor, and whereinthe first and second impedance control signals comprise respectiveanalog signals.
 46. The memory device of claim 40 wherein the at leastone PMOS transistor in the first control circuit and the at least onePMOS transistor coupled to each input terminal each comprise a pluralityof PMOS transistors coupled in parallel to each other, wherein the atleast one NMOS transistor in the second control circuit and the at leastone NMOS transistor coupled to each input terminal each comprise aplurality of NMOS transistors coupled in parallel to each other, andwherein the first and second impedance control signals compriserespective signals that selectively turn ON a variable number of thePMOS and NMOS transistors.
 47. The memory device of claim 40 wherein:the first comparator circuit comprises a first differential amplifiergenerating a first comparison signal corresponding to the differencebetween the first feedback signal and the first reference signal, thefirst impedance control signal corresponding to the first comparisonsignal; and the second comparator circuit comprises a seconddifferential amplifier generating a first comparison signalcorresponding to the difference between the second feedback signal andthe second reference signal, the second impedance control signalcorresponding to the second comparison signal.
 48. The memory device ofclaim 40 wherein the memory device comprises a dynamic random accessmemory.
 49. The memory device of claim 48 wherein the dynamic randomaccess memory comprises a synchronous dynamic random access memory. 50.A computer system, comprising: an integrated circuit processor having aplurality of externally accessible terminals coupled to a processor bus;an input device coupled to the processor through the processor busadapted to allow data to be entered into the computer system; an outputdevice coupled to the processor through the processor bus adapted toallow data to be output from the computer system; and an integratedcircuit memory device a plurality of externally accessible terminalscoupled to a processor bus; and an active termination circuit coupled toat least some of the externally accessible terminals, the activetermination circuit comprising: a first controllable impedance devicecoupled between a first supply voltage and a respective one of theexternally accessible terminals, the impedance of the first controllableimpedance device being controlled by a first impedance control signal; asecond controllable impedance device coupled between a second supplyvoltage and a respective one of the externally accessible terminals, theimpedance of the second controllable impedance device being controlledby a second impedance control signal; a first control circuit coupled toprovide the first impedance control signal to all of the firstcontrollable impedance devices, the first control circuit comprising: athird controllable impedance device coupled between a third supplyvoltage and a first feedback node, the impedance of the thirdcontrollable impedance device being controlled by the first impedancecontrol signal; a first predetermined resistance coupled between thefirst feedback node and a fourth supply voltage, the third controllableimpedance device and the first predetermined resistance forming avoltage divider between the third and fourth supply voltages to producea first feedback voltage at the first feedback node; and a firstcomparator circuit comparing the first feedback voltage to a firstreference voltage, the first comparator circuit causing the firstimpedance control signal to vary so that the first feedback voltage issubstantially equal to the first reference voltage; and a second controlcircuit coupled to provide the second impedance control signal to all ofthe second controllable impedance devices, the second control circuitcomprising: a second predetermined resistance coupled between a fifthsupply voltage and a second feedback node, a fourth controllableimpedance device coupled between the second feedback node and a sixthsupply voltage, the impedance of the fourth controllable impedancedevice being controlled by the second impedance control signal, thesecond predetermined resistance and the fourth controllable impedancedevice forming a voltage divider between the fifth and sixth supplyvoltages to produce a second feedback voltage at the second feedbacknode; and a second comparator circuit comparing the second feedbackvoltage to a second reference voltage, the second comparator circuitcausing the second impedance control signal to vary so that the secondfeedback voltage is substantially equal to the second reference voltage.51. The computer system of claim 50 wherein the command and addresssignals are coupled to the memory device in a packet containing both thecommand signals and the address signals.
 52. The computer system ofclaim 50 wherein the first, third and fifth supply voltages comprise apower supply voltage, and wherein the second, fourth, and sixth supplyvoltages comprise ground potential.
 53. The computer system of claim 50wherein the first and second reference voltages comprise one-half thepower supply voltage.
 54. The computer system of claim 50 wherein thefirst controllable impedance device and the third controllable impedancedevice comprise identical controllable impedance devices.
 55. Thecomputer system of claim 54 wherein the first controllable impedancedevice and the third controllable impedance device comprise identicalMOSFET transistors.
 56. The computer system of claim 50 wherein thesecond controllable impedance device and the fourth controllableimpedance device comprise identical controllable impedance devices. 57.The computer system of claim 56 wherein the first controllable impedancedevice and the third controllable impedance device comprise identicalMOSFET transistors.
 58. The computer system of claim 50 wherein: thefirst comparator circuit comprises a first differential amplifiergenerating a first comparison signal corresponding to the differencebetween the first feedback signal and the first reference signal, thefirst impedance control signal corresponding to the first comparisonsignal; and the second comparator circuit comprises a seconddifferential amplifier generating a first comparison signalcorresponding to the difference between the second feedback signal andthe second reference signal, the second impedance control signalcorresponding to the second comparison signal.
 59. The computer systemof claim 50 wherein the first controllable impedance device and thethird controllable impedance device each comprise a plurality of MOSFETtransistors coupled in parallel with each other, and wherein the firstimpedance control signal selectively turns ON a variable number of theMOSFET transistors in each plurality to alter the impedance of the firstand third controllable impedance devices.
 60. The computer system ofclaim 50 wherein the memory device comprises a dynamic random accessmemory.
 61. The computer system of claim 50 wherein the dynamic randomaccess memory comprises a synchronous dynamic random access memory. 62.The computer system of claim 50 wherein the controllable impedancedevices comprises respective voltage controlled impedance devices.
 63. Amethod of controlling the impedance of a plurality of input terminals ofan integrated circuit, the method comprising: comparing the impedance ofa first variable impedance device to a predetermined impedance; couplingeach of the input terminals to a respective second variable impedancedevice; and based on the comparison, adjusting the impedance of both thefirst variable impedance device and each of the second variableimpedance devices.
 64. The method of claim 63, further comprising:comparing the impedance of a third variable impedance device to a secondpredetermined impedance; coupling each of the input terminals to arespective fourth variable impedance device; and based on thecomparison, adjusting the impedance of both the third variable impedancedevice and each of the fourth variable impedance devices.
 65. The methodof claim 63 wherein the act of comparing the impedance of a firstvariable impedance device to a predetermined impedance comprisescoupling the first variable impedance device and the predeterminedimpedance in series with each other between a pair of reference voltagesto provide a feedback voltage at a node between the first variableimpedance device and the predetermined impedance.
 66. The method ofclaim 65 wherein the act of adjusting the impedance of both the firstvariable impedance device and each of the second variable impedancedevices comprises: comparing the feedback voltage to a referencevoltage; if the feedback voltage is larger than the reference voltage,adjusting the impedance of both the first variable impedance device andeach of the second variable impedance devices in a first direction; andif the feedback voltage is smaller than the reference voltage, adjustingthe impedance of both the first variable impedance device and each ofthe second variable impedance devices in a second direction that isopposite the first direction.
 67. The method of claim 63 wherein thefirst variable impedance device and the second variable impedancedevices each comprise a plurality of fixed impedance devices coupled inparallel with each other, and wherein the act of adjusting the impedanceof both the first variable impedance device and each of the secondvariable impedance devices comprises altering the number of fixedimpedance devices coupled in parallel with each other.
 68. The method ofclaim 63 wherein the first variable impedance device and the secondvariable impedance devices each comprise a plurality of switchableimpedance devices coupled in parallel with each other, each of theswitchable impedance devices having a low impedance state and a highimpedance state, and wherein the act of adjusting the impedance of boththe first variable impedance device and each of the second variableimpedance devices comprises altering the number of switchable impedancedevices having the low impedance state.
 69. The method of claim 63wherein the first variable impedance device and the second variableimpedance devices each comprise a continuously variable impedancedevice, and wherein the act of adjusting the impedance of both the firstvariable impedance device and the second variable impedance devicescomprises continuously varying the impedance of the continuouslyvariable impedance devices.
 70. In a memory device, a method ofcontrolling the input impedance of a plurality of externally accessibleinput terminals, the method comprising: coupling first and secondvariable impedance devices to each of the plurality of externallyaccessible input terminals; comparing the impedance of one of the firstvariable impedance devices to a first predetermined impedance; producinga first feedback signal corresponding to the comparison between theimpedance of the first variable impedance device and the firstpredetermined impedance; comparing the impedance of one of the secondvariable impedance devices to a second predetermined impedance;producing a second feedback signal corresponding to the comparisonbetween the impedance of the second variable impedance device and thesecond predetermined impedance; adjusting the impedance of all of thefirst variable impedance devices as a function of the first feedbacksignal; and adjusting the impedance of all of the second variableimpedance devices as a function of the second feedback signal.
 71. Themethod of claim 70 wherein the acts of adjusting the impedance of all ofthe first variable impedance devices as a function of the first feedbacksignal and adjusting the impedance of all of the second variableimpedance devices as a function of the second feedback signal comprise:comparing the magnitude of the first feedback signal to a firstreference voltage; if the magnitude of the first feedback signal isgreater than the first reference voltage, changing the impedance of thefirst variable impedance devices in a first direction; if the magnitudeof the first feedback signal is less than the first reference voltage,changing the impedance of the first variable impedance devices in asecond direction that is different from the first direction; comparingthe magnitude of the second feedback signal to a second referencevoltage; if the magnitude of the second feedback signal is greater thanthe second reference voltage, changing the impedance of the secondvariable impedance devices in a first direction; and if the magnitude ofthe second feedback signal is less than the second reference voltage,changing the impedance of the second variable impedance devices in asecond direction that is different from the first direction.
 72. Themethod of claim 70 wherein the variable impedance devices each comprisea plurality of fixed impedance devices coupled in parallel with eachother, and wherein the acts of adjusting the impedance of the variableimpedance devices comprise altering the number of fixed impedancedevices coupled in parallel with each other.
 73. The method of claim 70wherein the variable impedance devices each comprise a plurality ofswitchable impedance devices coupled in parallel with each other, eachof the switchable impedance devices having a low impedance state and ahigh impedance state, and wherein the acts of adjusting the impedance ofthe variable impedance devices comprise altering the number ofswitchable impedance devices having the low impedance state.
 74. Themethod of claim 70 wherein the variable impedance devices each comprisea continuously variable impedance device, and wherein the acts ofadjusting the impedance of the variable impedance devices comprisecontinuously varying the impedance of the continuously variableimpedance devices.